16.3 Virtual Address Translation
Avoiding TLB Conflict
Setting the TS bit in the Status register indicates an entry being presented to the TLB matches more than one virtual page entry in the TLB. Any TLB entries that allow multiple matches, even in the Wired area, are invalidated before the new entry can be written into the TLB. This prevents multiple matches during address translation.
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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